As CMOS technology continues to scale further into the sub-micron region, it becomes increasingly difficult to keep sufficiently low gate sheet resistance, low junction capacitance, and low junction depth of source/drain extensions under the gate. A conventional CMOS transistor 10 is shown in FIG. 1. Source/drain regions 14 are formed in a substrate 12. The polysilicon gate electrode 18 is separated from the substrate 12 by gate oxide layer 16. Sidewall dielectrics 20 are formed on the sidewalls of gate electrode 18. Transistor 10 typically includes source/drain extensions 22 that extend under sidewall dielectric 20.
As transistor 10 is scaled into the deep sub-micron region, the polysilicon gate 18 linewidths become narrower and narrower. This increases the gate sheet resistance. Achieving low gate sheet resistance becomes difficult even when silicided polysilicon is used. The source/drain junction regions 14 and source/drain extensions 22 must also become shallower to avoid undesired short-channel effects and roll-off of the threshold voltage at short channel lengths. However, in the deep sub-micron region, it is difficult to achieve shallower doping profiles by conventional means such as ion implantation. Therefore, there is a need for a CMOS transistor structure that can be scaled further into the sub-micron region while maintaining sufficiently low gate sheet resistance, small junction depth, and low junction capacitance.